(Not Applicable)
The present invention relates generally to chip stacks, and more particularly to a chip stack which employs the use of an anisotropic epoxy as an alternative to solder to facilitate the interconnection of the various components of the chip stack.
Multiple techniques are currently employed in the prior art to increase memory capacity on a printed circuit board. Such techniques include the use of larger memory chips, if available, and increasing the size of the circuit board for purposes of allowing the same to accommodate more memory devices or chips. In another technique, vertical plug-in boards are used to increase the height of the circuit board to allow the same to accommodate additional memory devices or chips.
Perhaps one of the most commonly used techniques to increase memory capacity is the stacking of memory devices into a vertical chip stack, sometimes referred to as 3D packaging or Z-Stacking. In the Z-Stacking process, from two (2) to as many as eight (8) memory devices or other integrated circuit (IC) chips are interconnected in a single component (i.e., chip stack) which is mountable to the xe2x80x9cfootprintxe2x80x9d typically used for a single package device such as a packaged chip. The Z-Stacking process has been found to be volumetrically efficient, with packaged chips in TSOP (thin small outline package) or LCC (leadless chip carrier) form generally being considered to be the easiest to use in relation thereto. Though bare dies or chips may also be used in the Z-Stacking process, such use tends to make the stacking process more complex and not well suited to automation.
In the Z-Stacking process, the IC chips or packaged chips must, in addition to being formed into a stack, be electrically interconnected to each other in a desired manner. There is known in the prior art various different arrangements and techniques for electrically interconnecting the IC chips or packaged chips within a stack. Examples of such arrangements and techniques are disclosed in Applicant""s U.S. Pat. No. 4,956,694 entitled INTEGRATED CIRCUIT CHIP STACKING issued Sep. 11, 1990, U.S. Pat. No. 5,612,570 entitled CHIP STACK AND METHOD OF MAKING SAME issued Mar. 18, 1997, and U.S. Pat. No. 5,869,353 entitled MODULAR PANEL STACKING PROCESS issued Feb. 9, 1999.
The various arrangements and techniques described in these issued patents and other currently pending patent applications of Applicant have been found to provide chip stacks which are relatively easy and inexpensive to manufacture, and are well suited for use in a multitude of differing applications. The chip stack disclosed in the parent application provides yet a further alternative arrangement and technique for forming a volumetrically efficient chip stack. In such chip stack, connections are routed from the bottom of the chip stack to the perimeter thereof so that interconnections can be made vertically which allows multiple integrated circuit chips such as BGA, CSP, fine pitch BGA, or flip chip devices to be stacked in a manner providing the potential for significant increases in the production rate of the chip stack and resultant reductions in the cost thereof.
In the above-described chip stacks, solder is the interconnect medium used to form the various interconnections between the components of the chip stacks. The current trend in electronics is for more functionality in a small device. This generally means more I/O""s in a smaller package. Interconnecting these smaller devices in turn requires a denser circuit board or other interconnection scheme. As the dimensions become smaller, the use of solder as the interconnect medium becomes increasingly less attractive. In this respect, smaller sizes require tighter control over such variables as solder paste and deposition, part geometries, reflow temperatures, etc. In these smaller devices, occurrences of solder bridging between neighboring interconnects becomes more common and difficult to control. Additionally, the smaller dimensions make post assembly cleaning very difficult. With regard to such cleaning, CFC""s are no longer allowed, with water washable flux being difficult to remove in small cavities due to the high surface tension of water. Either no-clean flux must be used or the chip stack assembly must be designed with cleaning objectives in mind.
In the assembly of chip stacks, the interest in lead-free solders is increasing and eventually will be required in Asia, Europe, and the United States. The most promising substitutes for tin/lead solder are based on tin-silver-copper-bismuth combinations which have melting points in excess of 200xc2x0 C. These melting points are substantially higher than traditional tin/lead solders, which melt at approximately 180xc2x0 C. These elevated melting points will require higher soldering temperatures. For packaged chip and flip chip assemblies, the higher melting points of lead-free solders may prove to be a concern, since these devices may not be able to withstand repeated elevated reflow temperatures. Further, the higher temperatures negate the use of a high temperature solder for subassemblies combined with a low temperature solder for attachment to a mother board.
The use of solder as an interconnect medium creates further challenges in relation to the three-dimensional stacking of devices. The rework of a stacked assembly becomes difficult, tedious, and labor intensive. Accordingly, the first pass yield must be high. Solder bridging or solder opens cannot be tolerated in such chip stacks.
The present invention eliminates many of the problems and challenges arising as a result of the use of solder as the interconnect medium by providing a chip stack and method of stacking integrated circuit (IC) devices using an anisotropic epoxy for the interconnections between the layers as an alternative to solder. Anisotropic epoxy consists of a fast cure epoxy containing small conductive particles uniformly dispersed within the epoxy component of the material. The density of particles is limited to the amount that does not cause contact from particle to particle. The epoxy may be in the form of a liquid or film. Typically, gold plated nickel particles of uniform size anywhere from five to ten microns in diameter are used. The liquid is dispensed or film placed between opposing conductive pads, with heat and pressure thereafter being applied. With pressure, particles are trapped between the conductive pads, thus forming a conductive conduit between the pads. The heat then cures the epoxy which holds the structure (i.e., layers) together. If the pads are nickel/gold plated, the particles form a pressure contact between the pads. If the pads are plated with a tin based metal and sufficient heat is applied, the particles form a metallugical connection between the pads. By controlling the size of the particles, bridging between adjacent pads can be eliminated, thus allowing for the achievement of fine pitch between the pads. Since flux is not used, post assembly cleaning is not required. Also, the composition of the particles does not include any toxic metal such as lead.
The processing window associated with the use of an anisotropic epoxy as the interconnect medium in the chip stack is very tolerant, with process temperatures being below 200xc2x0 C. Once cured, the anisotropic epoxy does not reflow at temperatures above 200xc2x0 C. Chip stacks assembled through the use of the anisotropic epoxy can be easily made using a panel format, then separating the stacks using standard PCB routing procedures. For example, typical panels 4 inches by 5xc2xd inches with multiple stack sites (16 or more on a panel)may be processed then stacked in a stacking fixture, and cured with heat and pressure as provided by a lamination press. The panels can easily be designed with multiple devices per layer for each resultant chip stack. Multiple devices such as BGA""s, TSOP""s, or bare die can be intermixed and placed on one base substrate. All interconnects between devices are made on the base substrate, with the I/O""s for that layer being terminated in conductive pads around the perimeter of the base substrate as with a single device. The stacking then proceeds as a single device on a layer. These and other advantages of the present invention will be discussed in more detail below.
In accordance with the present invention, there is provided a chip stack comprising at least two base layers (i.e., an upper base layer and a lower base layer). Each of the base layers includes a base substrate having a first conductive pattern disposed thereon. The chip stack further comprises at least one interconnect frame having a second conductive pattern disposed thereon. The interconnect frame is disposed between the upper and lower base layers, with the second conductive pattern being electrically connected to the first conductive pattern of each of the base layers via an anisotropic epoxy. In addition to the base layers and interconnect frame, the chip stack comprises at least two integrated circuit chips which are electrically connected to respective ones of the first conductive patterns via the anisotropic epoxy. The integrated circuit chip electrically connected to the first conductive pattern of the lower base layer is at least partially circumvented by the interconnect frame and at least partially covered by the upper base layer. The chip stack further preferably comprises a transposer layer which includes a transposer substrate having a third conductive pattern disposed thereon. The first conductive pattern of the lower base layer is electrically connected to the third conductive pattern of the transposer layer via the anisotropic epoxy.
In the present chip stack, the base substrate of each of the base layers defines opposed, generally planar top and bottom surfaces. The first conductive pattern itself comprises first and second sets of base pads which are disposed on the top surface of the base substrate, with the base pads of the second set being electrically connected to respective ones of the base pads of the first set via conductive traces. In addition to the first and second sets of base pads, the first conductive pattern includes a third set of base pads disposed on the bottom surface of the base substrate and electrically connected to respective ones of the base pads of the second set. More particularly, each of the base pads of the second set is preferably electrically connected to a respective one of the base pads of the third set via a base feed-through hole. The base feed-through hole may be plugged with a conductive material selected from the group consisting of nickel, gold, tin, silver epoxy, and combinations thereof. The integrated circuit chips are disposed upon respective ones of the top surfaces of the base substrates and electrically connected to at least some of the base pads of respective ones of the first sets via solder or the anisotropic epoxy. Additionally, the base pads of the second set of the lower base layer are electrically connected to the second conductive pattern of the interconnect frame via the anisotropic epoxy, as are the base pads of the third set of the upper base layer.
The interconnect frame of the chip stack itself defines opposed, generally planar top and bottom surfaces, with the second conductive pattern comprising first and second sets of frame pads disposed on respective ones of the top and bottom surfaces. Each of the frame pads of the first set is electrically connected to a respective one of the frame pads of the second set via a frame feed-through hole which also may be plugged with a conductive material preferably selected from the group consisting of nickel, gold, tin, silver epoxy, and combinations thereof. The interconnect frame is preferably disposed between the upper and lower base layers such that the frame pads of the second set are electrically connected to respective ones of the base pads of the second set of the lower base layer via the anisotropic epoxy, with the frame pads of the first set being electrically connected to respective ones of the base pads of the third set of the upper base layer via the anisotropic epoxy.
The transposer substrate of the present chip stack also defines opposed, generally planar top and bottom surfaces, with the third conductive pattern comprising first and second sets of transposer pads disposed on respective ones of the top and bottom surface of the transposer substrate. The transposer pads of the first set are electrically connected to respective ones of the transposer pads of the second set. Additionally, the base pads of the third set of the lower base layer are electrically connected to respective ones of the transposer pads of the first set via the anisotropic epoxy.
In the present chip stack, the transposer pads of the first set, the frame pads of the first and second sets, and the base pads of the second and third sets are preferably arranged identical patterns. Additionally, the transposer and base substrates each preferably have a generally rectangular configuration defining opposed pairs of longitudinal and lateral peripheral edge segments. The interconnect frame itself preferably has a generally rectangular configuration defining opposed pairs of longitudinal and lateral side sections. The transposer pads of the first set extend along the longitudinal and lateral peripheral edge segments of the transposer substrate. Similarly, the first and second sets of frame pads extend along the longitudinal and lateral side sections of the interconnect frame, with the second and third sets of base pads extending along the longitudinal and lateral peripheral edge segments of the base substrate. Each of the transposer pads of the second set preferably has a generally spherical configuration.
Each of the integrated circuit chips of the present chip stack preferably comprises a body having opposed, generally planar top and bottom surfaces, and a plurality of conductive contacts disposed on the bottom surface of the body. The conductive contacts of each of the integrated circuit chips are electrically connected to respective ones of the base pads of the first set of a respective one of the first conductive patterns. The electrical connection of the integrated circuit chips to respective ones of the first conductive patterns may be facilitated through the use of solder or through the use of the anisotropic epoxy. The transposer pads of the second set, the base pads of the first set, and the conductive contacts are themselves preferably arranged in identical patterns. When solder is used as the interconnect medium for the integrated circuit chips, the chip stack may further comprise a layer of flux/underfill (also referred to as a xe2x80x9cno flow-fluxing underfillxe2x80x9d) disposed between the bottom surface of the body of each of the integrated circuit chips and respective ones of the top surfaces of the base substrates. Each layer of flux/underfill may be spread over the base pads of the first set of a respective one of the first conductive patterns. The body of each of the integrated circuit chips and the interconnect frame are preferably sized relative to each other such that the top surface of the body of the integrated circuit chip electrically connected to the lower base panel and at least partially circumvented by the interconnect frame does not protrude beyond the top surface thereof.
The integrated circuit chips are preferably selected from the group consisting of a CSP (Chip Scale Package)such as a BGA (ball grid array) device, a fine pitch BGA device, and a flip chip device. However, the integrated circuit chips may also comprise LP (leaded plastic) devices or packages such as TSOP (thin small outline package) and TQFP devices. The integrated circuit chips may comprise bare die devices as well. Further, the transposer and base substrates are each preferably fabricated from a polyamide or other suitable circuit board material which may be as thin as about 0.010 inches.
Those of ordinary skill in the art will recognize that a chip stack of the present invention may be assembled to include more than two base layers, more than one interconnect frame, and more than two integrated circuit chips. In this respect, a multiplicity of additional interconnect frames, base layers, and integrated circuit chips may be included in the chip stack, with the second conductive pattern of each of the interconnect frames being electrically connected to the first conductive patterns of any adjacent pair of base layers via the anisotropic epoxy, and each of the integrated circuit chips being electrically connected to the first conductive pattern of a respective one of the base layers. Additionally, the chip stack of the present invention may be assembled to include differing types of integrated circuit chips, i.e., an intermix of different types of packaged chips and bare die devices in any combination.
Further in accordance with the present invention, there is provided a method of assembling a chip stack. The method comprises the initial step of electrically connecting an integrated circuit chip to a first conductive pattern of a base layer. The integrated circuit chip may be electrically connected to the base layer either through the use of solder or the anisotropic epoxy. Thereafter, a second conductive pattern of an interconnect frame is electrically connected to the first conductive pattern via the anisotropic epoxy such that the interconnect frame at least partially circumvents the integrated circuit chip. Another integrated circuit chip is then electrically connected to the first conductive pattern of another base layer. The first conductive pattern of one of the base layers is then electrically connected to the second conductive pattern of the interconnect frame via the anisotropic epoxy such that one of the integrated circuit chips is disposed between the base layers. The method may further comprise the step of electrically connecting the first conductive pattern of one of the base layers to a third conductive pattern of a transposer layer via the anisotropic epoxy. In the present assembly method, a layer of flux/underfill may be applied to (i.e., spread over) each of the base layers over portions of the first conductive patterns prior to the electrical connection of respective ones of the integrated circuit chips thereto.
Still further in accordance with the present invention, there is provided a method of assembling a chip stack which comprises the initial steps of providing a transposer panel, at least two base panels, and at least one frame panel which each have opposed surfaces and a plurality of conductive pads disposed on the opposed surfaces thereof. A plurality of integrated circuit chips are also provided which each have opposed sides and include conductive contacts disposed on one of the sides thereof. In this assembly method, an anisotropic epoxy is dispensed on at least some of the conductive pads of each of the transposer, base, and frame panels. Integrated circuit chips are then placed upon each of the base panels such that the conductive contacts of each of the integrated circuit chips are disposed on at least some of the conductive pads of respective ones of the base panels. Thereafter, one of the base panels is stacked upon the transposer panel such that at least some of the conductive pads of the base panel are disposed on at least some of the conductive pads of the transposer panel. The frame panel is then stacked upon the base panel such that at least some of the conductive pads of the frame panel are disposed on at least some of the conductive pads of the base panel. Another base panel is then stacked upon the frame panel such that at least some of the conductive pads of the base panel are disposed on at least some of the conductive of the frame panel.
The assembly method further comprises the step of placing the chip stack into a heated lamination press to cure the anisotropic epoxy, thereby securing the base panels, frame panel(s), and transposer panel to each other. The curing process also facilitates the bonding of the conductive contacts of the integrated circuit chips to the conductive pads of respective ones of base panels in the event the anisotropic epoxy is employed as the interconnect medium therebetween. As indicated above, solder may alternatively be used as the interconnect medium between the integrated circuit chips and the base panels. If solder is used as the interconnect medium, the integrated circuit chips 70 will typically be pre-attached to the base panels through a solder reflow process. The assembly method may further comprise the steps of stacking spacer sheets between one of the base panels and the transposer panel, and between the frame panel and each of the base panels. The spacer sheets each have opposed surfaces and a plurality of openings disposed therein. When stacked between the base and transposer panels and between the frame and base panels, the openings of the spacer sheets are aligned with the conductive pads of such panels.